Field of the Invention
The present invention particularly relates to a semiconductor device with a three-dimensional structure, and to a solid state imaging device.
Description of Related Art
In recent years, as solid state imaging devices, complementary metal oxide semiconductor (CMOS) type solid state imaging devices (hereinafter referred to as “MOS type solid state imaging devices”) have attracted attention and have been put into practical use. The MOS type solid state imaging devices can be driven by a single power source, unlike charge coupled device (CCD) type solid state imaging devices. Additionally, an exclusive manufacturing process is required in the CCD type solid state imaging devices, whereas the MOS type solid state imaging devices can be manufactured using the same manufacturing process as other LSIs. Therefore, dealing with a system on chip (SOC) is simple, and multiple functions of the solid state imaging devices are enabled. Additionally, the MOS type solid state imaging devices have a configuration in which these imaging devices are hardly influenced by noise from channels of communication of signals because signal charges are amplified within pixels by including an amplifying circuit in each pixel. Moreover, the MOS type solid state imaging devices have features in which it is possible for signal charges of respective pixels to be selected and taken out (selection system), and in principle, storage time and read-out order of signals can be freely controlled for each pixel.
Additionally, semiconductor devices of a stacked structure (three-dimensional structure) in which a plurality of substrates are three-dimensionally connected have attracted attention as dominant structures for maintaining improvements in the degree of integration in the semiconductor devices. In the semiconductor devices of the three-dimensional structure, for example, various barriers that semiconductor devices of a two-dimensional structure confront, such as the limitation of lithography in microfabrication, an increase in wiring resistance or an increase in a parasitic effect caused by the microfabrication of wiring or an increase in wiring length, the saturation tendency of the operating speed accompanied with these increases, and a high field effect caused by reduction of element dimensions, can be avoided by integrating semiconductor elements on a structure in which semiconductor active layers are three-dimensionally laminated in multilayer.
From this, in the related-art solid state imaging devices (hereinafter referred to as “imagers”), a monolithic structure was the mainstream design. In contrast, also in recent imagers, a three-dimensional structure has been put into practical use.
However, in the semiconductor devices of the three-dimensional structure, the influence of noise caused by wiring that connects the stacked substrates in accordance with an increase in the degree of integration cannot be avoided. Particularly, in the case of the imagers of the three-dimensional structure, a problem occurs in that an acquired image deteriorates due to the influence of the mixed in the wiring that connects the substrates. As a technique for solving such a problem, for example, a technique of providing shield wiring around penetration electrodes for connecting stacked substrates, thereby reducing the influence of noise, is suggested as disclosed in Japanese Unexamined Patent Application, First Publication No. 2012-089739.